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general description the maxq2010 microcontroller is a low-power, 16-bitdevice that incorporates a high-performance, 12-bit, multichannel adc and a liquid-crystal display (lcd) interface. a combination of high performance, low power, and mixed-signal integration makes the maxq2010 ideal for a wide variety of applications. the maxq2010 has 64kb of flash memory, 2kb of ram, three 16-bit timers, and two universal synchro- nous/asynchronous receiver/transmitters (usarts). flash memory aids prototyping and is available for mass production. mask rom versions are available for large production volumes when cost is a critical factor. the microcontroller runs from a 2.7v to 3.6v operating supply. for the ultimate in low-power performance, the maxq2010 includes a low-power sleep mode, the abili- ty to selectively disable peripherals, and multiple power-saving operating modes. applications features ? high-performance, low-power, 16-bit maxq risc core ? dc to 10mhz operation, approaching 1mips per mhz ? 2.7v to 3.6v operating voltage ? 33 instructions, most single cycle ? three independent data pointers accelerate datamovement with automatic increment/decrement ? 16-level hardware stack ? 16-bit instruction word, 16-bit data bus ? 16 x 16-bit general-purpose working registers ? optimized for c-compiler (high-speed/densitycode) ? on-chip fll reduces external clock frequency ? memory features 64kb flash memory (in-application and in-system programmable) 2kb internal data ramjtag bootloader for programming and debug ? peripheral features 12-bit sar adc with internal reference and autoscan eight single-ended or four differential inputsup to 312.5ksps sample rate supply voltage monitor with adjustable thresholdone-cycle, 16 x 16 hardware multiply/accumulate with 48-bit accumulator three 16-bit programmable timers/counters with pwm outputs 32-bit binary real-time clock with digital trim capability integrated lcd 160 segmentsno external resistors required two usarts, i 2 c master/slave, and spi master/ slave communications ports on-chip power-on reset/brownout resetprogrammable watchdog timer ? low power consumption 1ma (typ) at 1mhz flash operation at 2.7v370na (typ) in stop mode low-power power-management mode (pmm) maxq2010 16-bit mixed-signal microcontroller with lcd interface ________________________________________________________________ maxim integrated products 1 ordering information rev 1; 12/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package MAXQ2010-RFX+ -40 c to +85 c 100 lqfp typical application circuit, pin configuration, and selector guide appear at end of data sheet. maxq is a registered trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. battery-powered andportable devices portable medical equipment blood glucose meters electrochemical and optical sensors industrial control data-acquisition systems and data loggers home appliancesconsumer electronics thermostats/humidity sensors security sensors gas and chemical sensors hvac smart transmitters medical instrumentation downloaded from: http:///
absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 i 2 c electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 i 2 c bus controller timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 i 2 c bus controller timing (acting as i 2 c master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 i 2 c bus controller timing (acting as i 2 c slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 maxq core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 stack memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 utility rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 (bootloader) in-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 in-application programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 system timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 supply voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 serial peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 usart serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 programmable timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 hardware multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 in-circuit debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 grounds and bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 maxq2010 16-bit mixed-signal microcontroller with lcd interface 2 _______________________________________________________________________________________ table of contents downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface _______________________________________________________________________________________ 3 figure 1. spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 2. spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 3. series resistors (r s ) for protecting against high-voltage spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4. i 2 c bus controller timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 5. maxq2010 default memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 6. type c/d port pin schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 7. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 8. two-character, 1/2 duty, lcd interface example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 9. in-circuit debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 1. serial port operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 list of figures list of tables typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 development and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table of contents (continued) downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 4 _______________________________________________________________________________________ recommended dc operating conditions(v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on all pins (including avdd, dvdd) relative to ground .................................-0.5v to +3.6v voltage range on any pin relative to ground except avdd, dvdd .............-0.5v to (v dvdd + 0.5v) operating temperature range ...........................-40? to +85? continuous output current any single i/o pin ............................................................20ma all i/o pins combined....................................................100ma storage temperature range .............................-65? to +150? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units digital supply voltage v dvdd 2.7 3.6 v digital supply voltage output v regout (note 2) 1.8 v analog supply voltage v avdd v avdd = v dvdd 2.7 3.6 v ground gnd agnd = dgnd 0 0 v digital power-fail reset voltage v rst monitors v dvdd 2.55 2.6 2.65 v i dd_hfx1 f ck = 10mhz, v dvdd = v avdd = 2.7v, freqmd = 0 3.1 3.75 active current, fll disabled (note 3) i dd_hfx2 f ck = 10mhz, v dvdd = v avdd = 3.6v, freqmd = 0 (note 4) 3.2 4.0 ma i dd1_fll divide-by-1 mode, freqmd = 0 3.15 4 i dd2_fll divide-by-2 mode, freqmd = 0 (note 4) 2.9 3.6 i dd3_fll divide-by-4 mode, freqmd = 1 (note 4) 2.25 3 i dd4_fll divide-by-8 mode, freqmd = 1 (note 4) 1.4 2 active current, fll enabled (note 5) i dd5_fll pmm mode, freqmd = 1 (note 4) 0.5 0.7 ma t a = +25 c 0.37 4 i stop_1 (note 7) t a = +85 c 0.68 6.5 t a = +25 c 0.94 5 i stop_2 (note 8) t a = +85 c 1.3 6.5 t a = +25 c 195 295 stop-mode current (note 6) i stop_3 (note 9) t a = +85 c 225 335 a t stop_1 internal regulator on 4t clcl t stop_2 internal regulator off, brownout or svm on, svmstop = 1 30 160 stop-mode resume time (note 4) t stop_3 internal regulator, brownout, and svm off 30 320 s input low voltage on hfxin and 32kin v il1 dgnd 0.20 x v dvdd v input low voltage on all other pins v il2 dgnd 0.30 x v dvdd v absolute maximum ratings downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface _______________________________________________________________________________________ 5 recommended dc operating conditions (continued)(v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units input high voltage on hfxin and 32kin v ih1 0.75 x v dvdd v dvdd v input high voltage on all other pins v ih2 0.70 v dvdd v dvdd v input hysteresis (schmitt) v ihys 0.18 v output low voltage for all port pins (note 10) v ol i ol = +4ma dgnd 0.4 v output high voltage for all port pins (note 10) v oh i oh = -4ma v dvdd - 0.4 v i/o pin capacitance c io guaranteed by design 15 pf i/o pin capacitance scl, sda (note 11) c io_i2c guaranteed by design 10 pf rst pullup resistance r rst 30 85 k input low current for rst pin i il1 v in = 0.4v -85 -30 a input low current for all other pins i il2 v in = 0.4v -85 -30 a input leakage current i l internal pullup disabled -150 +150 na input pullup resistor r pu 30 85 k clock source external clock frequency f hfin dc 10 mhz external clock period t clcl 100 ns external clock duty cycle t xclk_duty 40 60 % system clock frequency f ck dc 10 mhz frequency-locked loop (fll) fll output frequency f fll f 32kin = 32.768khz 8.4 mhz fll output frequency delta f fll f 32kin = 32.768khz 1.5 5 % note 1: specifications to -40? are guaranteed by design and are not production tested. note 2: typical value presented for reference only. do not draw current from this pin. note 3: fll disabled. crystal connected across hfxin and hfxout. operating in divide-by-1 mode. measured on the dvdd pinand part executing program code from flash. all inputs are connected to gnd or dvdd. outputs do not source/sink any current. timer b enabled. note 4: this parameter is guaranteed by design and is not production tested. note 5: fll enabled. f 32kin = 32.768khz, hfxin = disconnected, fll = 8.39mhz, measured on the dvdd pin, part executing program code from flash. all inputs are connected to gnd or dvdd. outputs do not source/sink any current. timer benabled. note 6: i stop is the total current into the device when the device is in stop mode. this includes both the digital and analog current (current into dvdd and avdd). note 7: regulator, brownout monitor, lcd, and rtc disabled. note 8: regulator, brownout monitor, and lcd disabled; rtc enabled. note 9: regulator enabled, brownout monitor enabled, and lcd and rtc disabled. note 10: i oh(max) + i ol(max) for all outputs combined should not exceed 35ma to meet the specification. note 11: when dvdd is switched off, sda and scl may obstruct the line. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 6 _______________________________________________________________________________________ recommended dc operating conditions (continued)(v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units flash programming system clock during flash programming/erase 2 mhz mass erase 24 flash erase time page erase 24 ms flash programming time per word (note 12) 66 s write/erase cycles 20,000 cycles data retention t a = +25c 100 years analog-to-digital converter (note 13) serial clock frequency f sclk 0.1 5 mhz unipolar (single-ended) 0 v ref input voltage range v ain bipolar (differential) (note 14) -v ref /2 +v ref /2 v analog input capacitance c ain 16 pf i avdd1 f sclk = 5mhz, internal reference 1.9 2.5 current consumption (note 4) i avdd2 f sclk = 5mhz, external reference (internal reference disabled) 1.1 1.3 ma analog-to-digital converter performance (v ref = v avdd , 0.1f capacitor on v ref , f sclk = 5mhz) resolution 12 bits integral nonlinearity inl 1 2 lsb differential nonlinearity dnl no missing codes over temperatur e 1 lsb offset error vos 2 lsb offset temperature coefficient 0.5 ppm/c gain error 1 % gain temperature coefficient 0.5 ppm/c signal-to-noise plus distortion sinad f in = 1khz 65 db spurious-free dynamic range sfdr f in = 1khz 68 db throughput 16 sclk samples 312.5 ksps conversion time t conv not including t acq 2.6 s adc setup time t adc_setup (note 15) 4 s input leakage current i ila shutdown or conversion stopped, anx and v aeref 1 a autoscan throughput all channels active 39 ksps per channel analog-to-digital converter reference internal reference voltage v airef 1.47 1.5 1.53 v internal reference voltage startup time t airef 50 s downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface _______________________________________________________________________________________ 7 recommended dc operating conditions (continued)(v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units external reference voltage input v aeref 0.9 v avdd + 0.05 v internal reference voltage drift v adrift guaranteed by design 50 ppm/c reference settle time (switching adc reference from either internal or external reference to avdd) (note 16) t aavdd_ setup (note 17) 4 samples supply voltage monitor supply voltage set point v svm 2.7 3.5 v supply voltage increment resolution (note 18) sv inc 0.08 0.1 0.12 v supply voltage default set point 2.7 a supply voltage monitor current consumption i svm 20 s supply voltage monitor setup time (time from supply voltage monitor enabled to svmrdy is set to 1) (note 18) t svm_su 15 25 s real-time clock rtc input frequency f 32kin 32khz watch crystal 32,768 hz v dvdd = 2.7v, guaranteed by design 0.45 0.7 rtc operating current i rtc v dvdd = 3.6v 0.5 0.8 a lcd lcd reference voltage v lcd v dvdd 3.6 v lcd bias voltage 1 v lcd1 1/3 bias v adj + 2/3 (v lcd - v adj ) v lcd bias voltage 2 v lcd2 1/3 bias v adj + 2/3 (v lcd - v adj ) v lcd adjustment voltage v adj guaranteed by design 0 0.4 x v lcd v lcd bias resistor r lcd 40 k lcd adjustment resistor r ladj lra[3:0] = 15 80 k pin is driven at v lcd = 3v, i segxx = -3a v lcd - 0.02 v lcd pin is driven at v lcd1 = 2v, i segxx = -3a v lcd1 - 0.02 v lcd1 + 0.02 pin is driven at v lcd2 = 1v, i segxx = -3a v lcd2 - 0.02 v lcd2 + 0.02 lcd segment and com voltage (note 18) v segxx pin is driven at v adj = 0v, i segxx = -3a -0.1 +0.1 v lcd output rise time t lcd_rise com output load = 5000pf, seg output load = 200pf, v lcd = 3.3v 200 s downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 8 _______________________________________________________________________________________ note 12: programming time does not include overhead associated with the utility rom interface. note 13: v ref = v avdd . note 14: the operational input voltage range for each individual input of a differentially configured pair is from gnd to avdd. theoperational input voltage difference is from -v ref /2 to +v ref /2. note 15: the typical value is applied when a conversion is requested with adpmo = 0. under these conditions, the minimum delayis met. if adpmo = 1, the user is responsible for ensuring the 4? delay time is met. note 16: switching adc reference from either internal or external reference to avdd. sample accuracy is not guaranteed prior toadc reference settlement. note 17: total on-board decoupling capacitance on the avdd pin < 100nf. the output impedance of the regulator driving theavdd pin < 10 . note 18: this parameter is guaranteed by design and is not production tested. recommended dc operating conditions (continued)(v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units spi (see figures 1 and 2) spi master operating frequency 1/t mck f ck /2 mhz spi slave operating frequency 1/t sck f ck /8 mhz sclk output pulse-width high/low t mch , t mcl (t mck /2) - 25 ns sclk input pulse-width high/low t sch , t scl t sck /2 ns mosi output hold t ime after sclk sample edge t moh c l = 50pf (t mck /2) - 25 ns mosi output valid to sample edge t mov (t mck /2) - 25 ns miso input valid to sclk sample edge rise/fall setup t mis 25 ns miso input to sclk sample edge rise/fall hold t mih 0 ns sclk inactive to mosi inactive t mlh (t mck /2) - 25 ns ssel active to first shift edge t sse 4t ck ns mosi input to sclk sample edge rise/fall setup t sis 20 ns mosi input from sclk sample edge transition hold t sih t ck + 25 ns miso output valid after sclk shift edge transition t sov 3t ck + 25 ns ssel inactive t ssh t ck + 25 ns sclk inactive to ssel rising t sd t ck + 25 ns miso output disabled after ssel edge rise t slh 2t ck + 50 ns downloaded from: http:///
maxq2010 ssel shift shift sample sample mosimiso sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 t sch t scl t sis t sov t rf t sd t slh t ssh t sih t sse t sck msb msb-1 lsb msb lsb msb-1 ssel shift shift sample sample mosimiso sclk ckpol/ckpha 0/1 or 1/0 sclk ckpol/ckpha 0/0 or 1/1 t mck t mch t mcl t moh t mov t mis t mih t mlh t rf msb msb-1 msb msb-1 lsb lsb 16-bit mixed-signal microcontroller with lcd interface _______________________________________________________________________________________ 9 figure 2. spi slave timing figure 1. spi master timing downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 10 ______________________________________________________________________________________ i 2 c electrical characteristics (v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) note 19: devices that use nonstandard supply voltages that do not conform to the intended i 2 c bus system levels must relate their input levels to the voltage to which the pullup resistors r p are connected. see figure 3. note 20: c b ?apacitance of one bus line in pf. note 21: the maximum fall time of 300ns for the sda and scl bus lines shown in the i 2 c bus controller timing table is longer than the specified maximum t of_i2c of 250ns for the output stages. this allows series protection resistors (r s ) to be connected between the sda/scl pins and the sda/scl bus lines as shown in the i 2 c bus controller timing (acting as i 2 c slave) table without exceeding the maximum specified fall time. see figure 3. sda p6.7 scl p6.6 r s r s i 2 c device r s r s i 2 c device r p r p v dvdd maxq2010 figure 3. series resistors (r s ) for protecting against high-voltage spikes standard mode fast mode parameter symbol test conditions min max min max units input low voltage (note 19) v il_i2c -0.5 0.3 x v dvdd -0.5 0.3 x v dvdd v input high voltage (note 19) v ih_i2c 0.7 x v dvdd 0.7 x v dvdd v dvdd + 0.5v v input hysteresis (schmitt) v ihys_i2c v dvdd > 2v 0.05 x v dvdd v output logic-low (open drain or open collector) v ol_i2c v dvdd > 2v, 3ma sink current 0 0.4 0 0.4 v output fall time from v ih_min to v il_max with bus capacitance from 10pf to 400pf (notes 20, 21) t of_i2c 250 20 + 0.1c b 250 ns pulse width of spike filtering that must be suppressed by input filter t sp_i2c 0 50 ns input current on i/o i in_i2c input voltage from 0.1 x v dvdd to 0.9 x v dvdd -10 +10 -10 +10 a i/o capacitance c io_i2c 10 10 pf downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 11 i 2 c bus controller timing (v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 22) (figure 4) standard mode fast mode parameter symbol min max min max units operating frequency f i2c 0 100 0 400 khz hold time after (repeated) start t hd:sta 4.0 0.6 s clock low period t low_i2c 4.7 1.3 s clock high period t high_i2c 4.0 0.6 s setup time for repeated start t su:sta 4.7 0.6 s hold time for data t hd:dat 0 (note 23) 3.45 (note 24) 0 (note 23) 0.9 (note 24) s setup time for data t su:dat 250 100 (note 25) ns sda/scl fall time t f_i2c 300 20 + 0.1c b (note 26) 300 ns sda/scl rise time t r_i2c 1000 20 + 0.1c b (note 26) 300 ns setup time for stop t su:sto 4.0 0.6 s bus-free time between stop and start t buf 4.7 1.3 s capacitive load for each bus line c b 400 400 pf noise margin at the low level for each connected device (including hysteresis) v nl_i2c 0.1 x v dvdd 0.1 x v dvdd v noise margin at the high level for each connected device (including hysteresis) v nh_i2c 0.2 x v dvdd 0.2 x v dvdd v note 22: all values referenced to v ih_i2c(min) and v il_i2c(max) . note 23: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ih_i2c(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 24: the maximum t hd:dat need only be met if the device does not stretch the low period (t low_i2c ) of the scl signal. note 25: a fast-mode i 2 c bus device can be used in a standard-mode i 2 c bus system, but the requirement t su:dat 250ns must be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device doesstretch the low period of the scl signal, it must output the next data bit to the sda line t r_i2c(max) + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c specification) before the scl line is released. note 26: c b ?otal capacitance of one bus line in pf. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 12 ______________________________________________________________________________________ i 2 c bus controller timing (acting as i 2 c master) (v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (figure 4) standard mode fast mode parameter symbol min max min max units system frequency f sys 0.90 3.60 mhz operating frequency f i2c f sys /8 f sys /8 hz hold time after (repeated) start t hd:sta t high_i2c t high_i2c s clock low period t low_i2c 5t sys 5t sys s clock high period t high_i2c 3t sys 3t sys s setup time for repeated start t su:sta t low_i2c t low_i2c s hold time for data t hd:dat 0 3.45 0 0.9 s setup time for data t su:dat 250 100 ns sda/scl fall time t f_i2c 300 20+ 0.1c b 300 ns sda/scl rise time t r_i2c 1000 20+ 0.1c b 300 ns setup time for stop t su:sto t high_i2c t high_i2c s bus-free time between stop and start t buf t low_i2c t low_i2c s capacitive load for each bus line c b 400 400 pf noise margin at the low level for each connected device (including hysteresis) v nl_i2c 0.1 x v dvdd 0.1 x v dvdd v noise margin at the high level for each connected device (including hysteresis) v nh_i2c 0.2 x v dvdd 0.2 x v dvdd v downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 13 i 2 c bus controller timing (acting as i 2 c slave) (v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (figure 4) standard mode fast mode parameter symbol min max min max units system frequency f sys 0.9 3.60 mhz operating frequency f i2c f sys /8 f sys /8 hz system clock period t sys 1/f i2c 1 / f i2c s hold time after (repeated) start t hd:sta 3t sys 3t sys s clock low period t low_i2c 5t sys 5t sys s clock high period t high_i2c 3t sys 3t sys s setup time for repeated start t su:sta 5t sys 5t sys s hold time for data t hd:dat 0 3.45 0 0.9 s setup time for data t su:dat 250 100 ns sda/scl fall time t f_i2c 300 20 + 0.1c b 300 ns sda/scl rise time t r_i2c 1000 20 + 0.1c b 300 ns setup time for stop t su:sto 3t sys 3t sys s bus-free time between stop and start t buf 5t sys 5t sys s capacitive load for each bus line c b 400 400 pf noise margin at the low level for each connected device (including hysteresis) v nl_i2c 0.1 x v dvdd 0.1 x v dvdd v noise margin at the high level for each connected device (including hysteresis) v nh_i2c 0.2 x v dvdd 0.2 x v dvdd v sdascl ss r p s t f_i2c t r_i2c t low t high t hd:sta t su:dat t su:sta t su:sto t buf t hd:dat note: timing referenced to v ih_i2c(min) and v il_i2c(max) . figure 4. i 2 c bus controller timing diagram downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 14 ______________________________________________________________________________________ v dd supply current vs. clock frequency maxq2010 toc01 f hfxin (mhz) i dd1 (ma) 8 6 4 2 1.5 2.0 2.5 3.0 3.51.0 01 0 freqmd = 1 freqmd = 0 clock source driven on hfxin,t a = +25 c, fll disabled port pin low-output voltage vs. sink current maxq2010 toc02 v ol (v) i ol (ma) 3.2 2.8 0.4 0.8 1.2 2.0 1.6 2.4 5 10 15 20 25 30 35 40 0 0 3.6 t a = +25 c, v dvdd = 3.6v port pin high-output voltage vs. source current maxq2010 toc03 v oh (v) i oh (ma) 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 -50 -40 -30 -20 -10 0 -60 0 3.6 t a = +25 c, v dvdd = 3.6v integral nonlinearity (inl) vs. code maxq2010 toc04 code inl (lsb) 4000 3000 1000 2000 -1.5 -1.0 -0.5 0 1.00.5 1.5 2.0 -2.0 0 t a = +25 c, v avdd = 3.3v, v ref = 3.0v differential nonlinearity (dnl) vs. code maxq2010 toc05 code dnl (lsb) 4000 3000 2000 1000 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 t a = +25 c, v avdd = 3.3v, v ref = 3.0v offset error vs. supply voltage maxq2010 toc06 v dvdd (v) offset error (lsb) 3.56 3.46 3.06 3.16 3.26 3.36 -3 -2 -1 0 1 2 3 4 -4 2.96 3.66 t a = +25 c, v ref = 3.0v differential bipolar transfer maxq2010 toc07 input voltage (lsb) output code (hex) +fs 0 -fs 800 801 fff 000 001 7fe 7ff -fs + 0.5 lsb +fs - 0.5 lsb +fs = v ref /2 -fs = -v ref /2 1 lsb = v ref /4096 zs = 0 single-ended unipolar transfer maxq2010 toc08 input voltage (lsb) output code (hex) fs 2 3 4 1 001 002 003 004 ffd ffe fff 000 fs - 0.5 lsb fs = v ref 1 lsb = v ref /4096 zs = 0 typical operating characteristics (t a = +25?, unless otherwise noted.) downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 15 block diagram hfx fll 32khz 16 instruction decoder program memory data memory control stack add reg address generator demux mux ip dp spr in-circuit debugger sfr acc status jtag interrupt supply voltage monitor mac watchdog power osc up brownout reset lcd dvdddgnd avdd agnd 12-bit 8-channel adc i 2 c rtc spi reset pmm stop system clock 16 timer uart maxq2010 downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 16 ______________________________________________________________________________________ pin description pin name function power pins 40, 63, 96 dvdd digital supply voltage 41, 66, 95 dgnd digital ground 98, 99 regout regulator capacitor. these pins must be shorted together at the pins and then connected to ground through a 1.0f ceramic capacitor. 82 avdd analog supply voltage 79 agnd analog ground analog measurement pins 70 avref analog voltage reference. when using an external reference source, this pin must be connected to 1f and 0.01f filter capacitors in parallel. when using an internal reference source, this pin must be connected to a 0.01f capacitor. 78, 77 an0, an1 analog input 0:1. this pair of analog inputs can function as two single-ended inputs or one differential pair. when functioning in differential mode, an0 is th e positive input and an1 is the negative input. 76, 75 an2, an3 analog input 2:3. this pair of analog inputs can function as two single-ended inputs or one differential pair. when functioning in differential mode, an2 is th e positive input and an3 is the negative input. 74, 73 an4, an5 analog input 4:5. this pair of analog inputs can function as two single-ended inputs or one differential pair. when functioning in differential mode, an4 is th e positive input and an5 is the negative input. 72, 71 an6, an7 analog input 6:7. this pair of analog inputs can function as two single-ended inputs or one differential pair. when functioning in differential mode, an6 is th e positive input and an7 is the negative input. reset pin 92 rst digital, active-low, reset input/output. the cpu is held in reset when this pin is low and begins executing from the reset vector when released. the pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 4ma. this pin is driven low as an output when an internal reset conditi on occurs. clock pins 81 32kin 80 32kout 32khz crystal input/output. connect an external 6pf, 32khz watch crystal between 32kin and 32kout to generate the system clock. alternatively, 32kin is the input for an external clock source when 32kout is disconnected. 64 hfxin 65 hfxout high-frequency crystal input . connect an external crystal or resonator between hfxin and hfxout as the high-frequency system clock. alternatively, hfxin i s the input for an external, high-frequency clock source when hfxout is disconnected. lcd pins 45 v lcd lcd bias control voltage . highest lcd drive voltage used with static bias. connected to an external source. 44 v lcd1 lcd bias, voltage 1. lcd drive voltage used with 1/2 and 1/3 lcd bias. an internal resistor- divider sets the voltage. external resistors and capacitors can b e used to change the lcd voltage or drive capability at this pin. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 17 pin description (continued) pin name function 43 v lcd2 lcd bias, voltage 2. lcd drive voltage used with 1/3 lcd bias. an internal resistor-d ivider sets the voltage. external resistors and capacitors can be used to change lcd voltage or drive capability at this pin. 42 v adj lcd adjustment voltage. connect to an external resistor to provide external control of the lcd contrast. leave disconnected for internal contrast adjustment. general-purpose i/o, special function, and lcd interface pins digital i/o, type d port 0; lcd segment-driver output; external edge -selectable interrupt. this port functions as either bidirectional i/o or alternate lcd segment-drive outputs. the reset condition of the port is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition serves as an input mode. each port pin can individually be configured to act as an external interrupt. setting the pcf0 bit switches all pins on this port to lcd segment-drive outputs. it is possible to mix the lcd and interrupt functions on the same po rt. to do this, the interrupt enable must be established prior to setting the pcf0 bit. care must be ta ken not to enable the external interrupt while the lcd is in normal operational mode, as this could result in potentially harmful contention between the lcd controller output and the external source connected to the interrupt input. pin port special/alternate function 6 p0.0 seg0 int0 5 p0.1 seg1 int1 4 p0.2 seg2 int2 3 p0.3 seg3 int3 2 p0.4 seg4 int4 1 p0.5 seg5 int5 94 p0.6 seg6 int6 6C1, 94, 93 p0.0Cp0.7; seg0Cseg7; int0Cint7 93 p0.7 seg7 int7 digital i/o, type c port 1; lcd segment-driver output. this port functions as either bidirectional i/o or alternate lcd segment-drive outputs. the rese t condition of the port is with all bits at logic 1. in this state, a weak pullup holds the port high. thi s condition serves as an input mode. the port pins also contain a schmitt voltage inpu t. setting the pcf1 bit switches all pins on this port to lcd segment-drive outputs. pin port special/alternate function 91 p1.0 seg8 90 p1.1 seg9 89 p1.2 seg10 88 p1.3 seg11 87 p1.4 seg12 86 p1.5 seg13 85 p1.6 seg14 91C84 p1.0Cp1.7; seg8Cseg15 84 p1.7 seg15 downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 18 ______________________________________________________________________________________ pin description (continued) pin name function digital i/o, type c port 2; lcd segment-driver output. this port functions as either bidirectional i/o or alternate lcd segment-drive outputs. the rese t condition of the port is with all bits at logic 1. in this state, a weak pullup holds the port high. thi s condition serves as an input mode. the port pins also contain a schmitt voltage inpu t. setting the pcf2 bit switches all pins on this port to lcd segment-drive outputs. pin port special/alternate function 56 p2.0 seg16 55 p2.1 seg17 54 p2.2 seg18 53 p2.3 seg19 52 p2.4 seg20 48 p2.5 seg21 47 p2.6 seg22 56C52, 48C46 p2.0Cp2.7; seg16Cseg23 46 p2.7 seg23 digital i/o, type c port 3; lcd segment-driver output. this port functions as either bidirectional i/o or alternate lcd segment-drive outputs. the rese t condition of the port is with all bits at logic 1. in this state, a weak pullup holds the port high. thi s condition serves as an input mode. the port pins also contain a schmitt voltage inpu t. setting the pcf3 bit switches all pins on this port to lcd segment-drive outputs. pin port special/alternate function 36 p3.0 seg24 35 p3.1 seg25 34 p3.2 seg26 33 p3.3 seg27 22 p3.4 seg28 21 p3.5 seg29 20 p3.6 seg30 36C33, 22C19 p3.0Cp3.7; seg24Cseg31 19 p3.7 seg31 digital i/o, type-c port 4; lcd segment-driver output. this port functions as either bidirectional i/o or alternate lcd segment-drive outputs. the rese t condition of the port is with all bits at logic 1. in this state, a weak pullup holds the port high. thi s condition serves as an input mode. the port pins also contain a schmitt voltage inpu t. setting the pcf4 bit switches all pins on this port to lcd segment-drive outputs. pin port special/alternate function 18 p4.0 seg32 17 p4.1 seg33 16 p4.2 seg34 15 p4.3 seg35 14 p4.4 seg36 13 p4.5 seg37 12 p4.6 seg38 18C11 p4.0Cp4.7; seg32Cseg39 11 p4.7 seg39 downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 19 pin description (continued) pin name function lcd segment-driver output; lcd common drive output. these pins function as lcd segment or common drive outputs. configuring a pin as a common drive ou tput disables the segment function for that pin. pin special/alternate function 10 com3 seg40 9 com2 seg41 10, 9, 8 com3, com2, com1; seg40, seg41, seg42 8 com1 seg42 7c o m 0 lcd common drive 0, output. this pin functions as a lcd common-drive output. 68 p5.0/int8/ tb0b/rx0 digital i/o, type d port 5.0; timer b0 pin b; serial port 0 receive; ext ernal edge-selectable interrupt 8. this pin defaults to an input with a weak pullup after reset and funct ions as general-purpose i/o. the port pad contains a schmitt voltage input a nd can be configured as an external interrupt. enabling a special function disables the pin as digital i/o. 67 p5.1/int9/ tb0a/tx0 digital i/o, type d port 5.1; timer b0 pin a; serial port 0 transmit; ex ternal edge- selectable interrupt 9. this pin defaults to an input with a weak pullup after reset and functions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured as an external interrupt. enabling a special function di sables the pin as general- purpose i/o. 61 p5.2/int10/ sqw digital i/o, type-d port 5.2; external edge-selectable interrupt 10; rtc sq uare-wave output. this pin defaults to an input with a weak pullup after reset and fun ctions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured a s an external interrupt. enabling a special function disables the pin as general-p urpose i/o. 60 p5.3/int11/ ssel digital i/o, type d port 5.3; external edge-selectable interrupt 11; active- low spi slave- select input. this pin defaults to an input with a weak pullup after reset and funct ions as general-purpose i/o. the port pad contains a schmitt voltage input a nd can be configured as an external interrupt. enabling a special function disables the pin as general-purpose i/o. 59 p5.4/int12/ mosi digital i/o, type d port 5.4; external edge-selectable interrupt 12; spi ma ster out-slave in. this pin defaults to an input with a weak pullup after reset and fun ctions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured a s an external interrupt. enabling a special function disables the pin as general-p urpose i/o. 58 p5.5/int13/ sclk digital i/o, type d port 5.5; external edge-selectable interrupt 13; spi cl ock output. this pin defaults as an input with a weak pullup after a reset and functions as general-purpose i/o. the port pad contains a schmitt input circuitry and can be configured as an external interrupt. enabling a special function disables the pin as general-purpose i/o . 57 p5.6/int14/ miso digital i/o, type d port 5.6; external edge-selectable interrupt 14; spi ma ster in-slave out. this pin defaults to an input with a weak pullup after reset and fun ctions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured a s an external interrupt. enabling a special function disables the pin as general-p urpose i/o. 32 p6.0/int15/ tck digital i/o, type d port 6.0; external edge-selectable i nterrupt 15; jtag test clock input. this pin defaults to an input with a weak pullup after reset and fun ctions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured a s an external interrupt. enabling a special function disables the pin as general-p urpose i/o. 31 p6.1/int16/ tdi digital i/o, type d port 6.1; external edge-selectable interrupt 16; jtag t est data input. this pin defaults to an input with a weak pullup after reset and fun ctions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured a s an external interrupt. enabling a special function disables the pin as general-p urpose i/o. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 20 ______________________________________________________________________________________ pin description (continued) pin name function 30 p6.2/int17/ tms digital i/o, type d port 6.2; external edge-selectable interrupt 17; jtag t est mode select input. this pin defaults to an input with a weak pullup after reset and func tions as general- purpose i/o. the port pad contains a schmitt voltage input and ca n be configured as an external interrupt. enabling a special function disables the pin as gene ral-purpose i/o. 29 p6.3/int18/ tdo digital i/o, type-d port 6.3; external edge-selectable interrupt 18; jtag t est data output. this pin defaults to an input with a weak pullup after reset and fun ctions as general-purpose i/o. the port pad contains a schmitt voltage input and can be configured a s an external interrupt. enabling a special function disables the pin as general-p urpose i/o. 28 p6.4/int19/ tb1b/rx1 digital i/o, type d port 6.4; external edge-selectable interrupt 19; time r b1 pin b; serial port 1 receive. this pin defaults to an input with a weak pullup after reset and function s as general-purpose i/o. the port pad contains a schmitt voltage input a nd can be configured as an external interrupt. enabling a special function disables the pin as general-purpose i/o. 25 p6.5/int20/ tb1a/tx1 digital i/o, type d port 6.5; external edge-selectable interrupt 20; time r b1 pin a; serial port 1 transmit. this pin defaults to an input with a weak pullup after reset and funct ions as general-purpose i/o. the port pad contains a schmitt voltage input a nd can be configured as an external interrupt. enabling a special function disables the pin as general-purpose i/o. 24 p6.6/int21/ tb2b/scl digital i/o, type d port 6.6; external edge-selectable interrupt 21; time r b2 pin b; i 2 c clock i/o. this pin defaults to an input with a weak pullup after reset and fu nctions as general- purpose i/o. the port pad contains a schmitt voltage input and ca n be configured as an external interrupt. enabling a special function disables the pin as gene ral purpose i/o. 23 p6.7/int22/ tb2a/sda digital i/o, type d port 6.7; external edge-selectable interrupt 22; time r b2 pin a; i 2 c data i/o. this pin defaults to an input with a weak pullup after reset and fu nctions as general- purpose i/o. the port pad contains a schmitt voltage input and ca n be configured as an external interrupt. enabling a special function disables the pin as gene ral-purpose i/o. no connection pins 26, 27, 37, 38, 39, 49, 50, 51, 62, 69, 83, 97, 100 n.c. no connection. reserved for future use. leave these pins unconnected. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 21 detailed description the following sections are an introduction to the prima-ry features of the microcontroller. more detailed descriptions of the device features can be found in the errata sheets and user? guides described later in the additional documentation section. maxq core architecture the maxq2010 is a low-cost, high-performance,cmos, fully static, 16-bit risc microcontroller with flash memory and an integrated lcd controller. the maxq2010 supports up to a 160-segment lcd and supports 8 channels of high-performance measurement using a 12-bit successive approximation register (sar) adc with internal reference. the maxq2010 is struc- tured on a highly advanced, accumulator-based, 16-bit risc architecture. fetch and execution operations are completed in one cycle without pipelining because the instruction contains both the op code and data. the result is a streamlined microcontroller performing at up to one million instructions-per-second (mips) for each mhz of the system operating frequency. a 16-level hardware stack, enabling fast subroutine calling and task switching, supports the highly efficient core. data can be quickly and efficiently manipulated with three internal data pointers. multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. as a result, application speed is greatly increased. instruction set the instruction set is composed of fixed-length, 16-bitinstructions that operate on registers and memory loca- tions. the instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. special-function registers control the peripherals and are subdivided into register modules. the family architecture is modular so that new devices and modules can reuse code developed for existing products. the architecture is transport-triggered, which means that writes or reads from certain register locations can also cause side effects to occur. these side effects form the basis for the higher level op codes defined by the assembler, such as addc, or, jump, etc. the op codes are actually implemented as move instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. the 16-bit instruction word is designed for efficient exe-cution. bit 15 indicates the format for the source field of the instruction. bits 0 to 7 of the instruction represent the source for the transfer. depending on the value of the format field, this can either be an immediate value or a source register. if this field represents a register, the lower four bits contain the module specifier and the upper four bits contain the register index in that mod- ule. bits 8 to 14 represent the destination for the trans- fer. this value always represents a destination register, with the lower four bits containing the module specifier and the upper three bits containing the register subindex within that module. any time that it is neces- sary to directly select one of the upper 24 registers as a destination, the prefix register (pfx) is needed to sup- ply the extra destination bits. this prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. memory organization the device incorporates several memory areas, includ-ing: ?4kb utility rom ?64kb of flash memory for program storage ?2kb of sram for storage of temporary variables ?16-level stack memory for storage of program return addresses and general-purpose use the incorporation of flash memory allows the devices tobe reprogrammed multiple times, allowing modifica- tions to user applications post production. additionally, the flash can be used to store application information including configuration data and log files. the default memory organization is organized as a harvard architecture, with separate address spaces for program and data memory. pseudo-von neumann memory organization is supported through the utility rom for applications that require dynamic program modification and execution from ram. the pseudo-von neumann memory organization places the code, data, and utility rom memories into a single contiguous memory map. see figure 5 for the memory map. stack memory a 16-bit-wide hardware stack provides storage for pro-gram return addresses and can also be used as gener- al-purpose data storage. the stack is used automatically by the processor when the call, ret, and reti instructions are executed and when an inter- rupt is serviced. an application can also store values in the stack explicitly by using the push, pop, and popi instructions. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 22 ______________________________________________________________________________________ on reset, the stack pointer, sp, initializes to the top ofthe stack (0fh). the call, push, and interrupt-vector- ing operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value at sp and then decrement sp. utility rom the utility rom is a 4kb block of internal rom memorythat defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software. these include the following: in-system programming (bootstrap loader) using jtag interface ?in-circuit debug routines ?test routines (internal memory tests, memory loader, etc.) user-callable routines for in-application flash pro- gramming and fast table lookup following any reset, execution begins in the utility rom.the rom software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the spe- cial routines mentioned. routines within the utility rom are user-accessible and can be called as subroutines by the application software. more information on the utility rom contents is contained in the maxq family user? guide: maxq2010 supplement . some applications require protection against unautho-rized viewing of program code memory. for these program space data space 2k x 16 utility rom 1k x 16 data ram 32k x 16 program memory 8000h 00h 0fh ffffh wbsn = 1 ffffh wbsn = 0ffffh 07ffh 03ffh 0000h 0000h 87ffh7fffh 0000h 0fh07h 06h 00h 1fh sprs sfrs registers ffh 16 x 16 stack figure 5. maxq2010 default memory map downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 23 applications, access to in-system programming, in-application programming, or in-circuit debugging func- tions is prohibited until a password has been supplied. the password is defined as the 16 words of physical program memory at addresses 0010h to 001fh. a single password lock (pwl) bit is implemented in the sc register. when the pwl is set to 1 (power-on reset default) and the contents of the memory at addresses 0010h to 001fh are any value other than all ffh or 00h, the password is required to access the utility rom, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. when pwl is cleared to 0, these utilities are fully acces- sible without the password. the password is automati- cally set to all 1s following a mass erase. programming the microcontroller? flash memory can be pro-grammed by two different methods: in-system program- ming and in-application programming. both methods afford great flexibility in system design and reduce the life-cycle cost of the embedded system. these features can be password protected to prevent unauthorized access to code memory. (bootloader) in-system programming an internal bootstrap loader allows the device to bereloaded over a simple jtag interface. as a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. remote software updates enable application updates to physically inaccessible equipment. the interface hardware can be a jtag connection to anoth- er microcontroller, or a connection to a pc serial port using a serial-to-jtag converter such as the maxqj- tag-001, available from maxim. if in-system program- mability is not required, use a commercial gang programmer for mass programming. activating the jtag interface and loading the test access port (tap) with the system programming instruction invokes the bootstrap loader. setting the spe bit to 1 during reset through the jtag interface exe- cutes the bootstrap-loader-mode program that resides in the utility rom. when programming is complete, the bootstrap loader can clear the spe bit and reset the device, allowing the device to bypass the utility rom and begin execution of the application software. the following bootstrap loader functions are supported: ?load ?verify ?dump ?erase ?crc in-application programming the in-application programming feature allows themicrocontroller to modify its own flash program memory while simultaneously executing its application software. this allows on-the-fly software updates in mission-criti- cal applications that cannot afford downtime. alternatively, it allows the application to develop cus- tom loader software that can operate under the control of the application software. the utility rom contains user-accessible flash programming functions that erase and program flash memory. these functions are described in detail in the maxq family user? guide: maxq2010 supplement . register set most functions of the device are controlled by sets ofregisters. these registers provide a working space for memory operations as well as configuring and address- ing peripheral registers on the device. registers are divided into two major types: system registers and peripheral registers. the common register set, also known as the system registers, includes the alu, accu- mulator registers, data pointers, interrupt vectors and control, and stack pointer. the peripheral registers define additional functionality that may be included by different products based on the maxq architecture. this functionality is broken up into discrete modules so that only the features required for a given product need to be included. the documentation on the module and register func- tions is covered fully in the maxq family user? guide and the maxq family user? guide: maxq2010 supplement . this information includes the locations of status and control bits and a detailed description oftheir function and reset values. refer to these docu- ments for a complete understanding of the features and operation of the microcontroller. system timing for maximum versatility, the device can generate itsinternal system clock from several sources: ?external clock source ?internal oscillator using external crystal or resonator ?fll using 32khz clock source (approximately 8mhz) ?fll with no external crystal (approximately 5mhz) operation from an external clock source or internal oscillator using external crystal or resonator is similar to other microcontrollers. the designer must remember that the rated maximum speed of operation applies to the speed of the microcontroller core, not the external downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 24 ______________________________________________________________________________________ clock source. the device contains an fll that is usedas a clock source by itself (fllen = 0) or as a multipli- er for the 32khz crystal (fllen = 1). the 32khz-mode- based timing is more stable due to the use of the crystal as a time base. a crystal warmup counter enhances operational reliabil- ity. if the user has selected to run from the external crystal or clock source, each time the external crystal oscillation must restart, such as after exiting stop mode, the device initiates a crystal warmup period of 65,536 oscillations. this allows time for the crystal amplitude and frequency to stabilize before using it as a clock source. while in the warmup mode, the device operates from the internal fll and automatically switches back to the crystal as soon as it is ready. programmable clock-divide control bits (cd1 and cd0) and the pmme bit provide the processor with the ability to slow the system clock, resulting in lower power con- sumption. the cd[1:0] bits default to 00b, selecting a divide-by-1 system clock, but five clock-divisor options allow the selection of different crystals to accommodate specific system needs. in power-management mode (pmm), one system clock is 256 oscillator cycles, signif- icantly reducing power consumption while the micro- controller functions at reduced speed. the switchback feature allows the system to exit pmm in response to an external interrupt or serial port activity, quickly switch- ing from the slower, power-saving mode to full speed. in addition, the lowest power stop mode allows the microcontroller to stop the internal oscillator, halting the system clock. interrupts multiple interrupt sources are available for quickresponse to internal and external events. the maxq architecture uses a single interrupt vector (iv), single interrupt-service routine (isr) design. for maximum flex- ibility, interrupts can be enabled globally, individually, or by the module. when an interrupt condition occurs, its individual flag is set, even if the interrupt source is dis- abled at the local, module, or global level. interrupt flags must be cleared within the user-interrupt routine to avoid repeated interrupts from the same source. application software must ensure a delay between the write to the flag and the reti instruction to allow time for the interrupt hardware to remove the internal inter- rupt condition. asynchronous interrupt flags require a one-instruction delay, and synchronous interrupt flags require a two-instruction delay. when an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. the iv register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user pro-gram must determine whether a jump to 0000h came from a reset or interrupt source. once software control has been transferred to the isr, the interrupt identification register (iir) can be used to determine if a system register or peripheral register was the source of the interrupt. the specified module can then be interrogated for the specific interrupt source and software can take appropriate action. because the user software evaluates the interrupts, the user can define a unique interrupt priority scheme for each application. the following interrupt sources are supported: ?supply voltage monitor ?external interrupts 22 to 0 ?timer 2, 1, 0 ?serial port 1, 0 ?watchdog timer ?rtc time-of-day or subsecond alarm ?spi ?i 2 c ?adcwhen an enabled interrupt is detected, software jumps to the dedicated interrupt vector address reserved for that interrupt. user-application code at this address then routes program execution to a user-defined inter- rupt routine. i/o ports the microcontroller uses type c and type d bidirec-tional i/o pins as described in the maxq family user's guide . each port has up to eight independent, general- purpose i/o pins and three configure/control registers.many pins support alternate functions such as timers or interrupts, which are enabled, controlled, and monitored by dedicated peripheral registers. using the alternate function automatically converts the pin to that function, overriding the general-purpose i/o functionality. type c port pins have schmitt trigger receivers and full cmos output drivers, and can support alternate func- tions. the pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. type d port pins have schmitt trigger receivers and full cmos output drivers, and can support alternate func- tions. the pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. all type d pins also have interrupt capability. see figure 6 for a type c/d port pin schematic. downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 25 supply voltage monitor the supply voltage monitor can detect if the supply volt-age has fallen below a user-selectable level. if this hap- pens, the microcontroller can be programmed to generate an interrupt to inform the system. the detec- tion level is set using the supply voltage threshold bit (svth) and can be adjusted from 2.7v to 3.5v in 0.1v increments. setting the svmen bit to 1 enables the sup- ply voltage monitor. once the monitoring circuitry is sta- ble and ready for operation, the supply voltage monitor ready (svmrdy) flag is set to 1. the default set point is 2.7v (svth[3:0] = 07h). care must be taken not to set the set point below 2.7v as svm interrupts may not occur because the brownout monitor may activate first. the supply voltage monitor causes a switchback to occur if the supply voltage falls below the threshold value and the supply voltage monitor interrupt is enabled (svmie = 1). the supply voltage monitor remains operational in stop mode if the supply voltage monitor stop mode enable bit (svmstop) is set to 1. clearing svmstop to 0 dis-ables the supply voltage monitor on entry to stop mode if the svm peripheral is enabled. if the supply voltage monitor is enabled during stop mode, an svmi interrupt causes the processor to exit stop mode if enabled (svmie = 1). serial peripherals the microcontroller supports two independent usartsas well as i 2 c master/slave and spi master communi- cation ports. usart serial ports the independent usarts provide transmit and receivesignals to communicate with other rs-232 interface- enabled devices, as well as pcs and serial modems when paired with an external rs-232 line driver/receiver. the dual independent usarts can communicate simulta- neously at different baud rates with two separate periph- erals. the usart can detect framing errors and indicate the condition through a user-accessible software bit. pd.x sf direction sf enable mux mux po.x v ddio sf output v ddio weak i/o pad port pin interrupt flag flag pi.x or sf input eies.x type d port only detect circuit maxq2010 figure 6. type c/d port pin schematic downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 26 ______________________________________________________________________________________ the time base of the serial ports is derived from either adivision of the system clock or the dedicated baud- clock generator. table 1 summarizes the operating characteristics of each mode. i 2 c bus the microcontroller integrates an internal i 2 c bus mas- ter/slave for communication with a wide variety of otheri 2 c-enabled peripherals. the i 2 c bus is a 2-wire bidi- rectional bus using two bus lines, the serial data line(sda), and the serial clock line (scl), as well as a ground line. both the sda and scl lines must be dri- ven as open-collector/drain outputs. external resistors are required as shown in figure 3 to pull the lines to a logic-high state. the maxq2010 is flexible in that it supports both the master and slave protocols. in the master mode, the device has ownership of the i 2 c bus and drives the clock and generates the start and stop signals. thisallows it to send data to a slave or receive data from a slave as required. in slave mode, the maxq2010 relies on an externally generated clock to drive scl and responds to data and commands only when requested by the i 2 c master device. serial peripheral interface (spi) the integrated spi provides an independent serialcommunication channel that communicates synchro- nously with peripheral devices in a multiple master or multiple slave system. the interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. collision detection is provided when two or more masters attempt a data transfer at the same time. the maximum spi master transfer rate is sysclk/2. when operating as an spi slave, the maxq2010 can support up to a sysclk/4 spi transfer rate. data is trans- ferred as an 8-bit or 16-bit value, msb first. in addition, the spi module supports configuration of active ssel state through the slave-active select. real-time clock a binary real-time clock (rtc) keeps the time of day inabsolute seconds with 1/256-second resolution. the 32-bit second counter can count up to approximately 136 years and be translated to calendar format by application software. a time-of-day alarm and indepen- dent subsecond alarm can cause an interrupt or wake the device from stop mode. the independent subsecond alarm runs from the same rtc and allows the application to support interrupts with a minimum interval of approximately 3.9ms. this creates an additional timer that can be used to mea- sure long periods of time without performance degra- dation. traditionally, long time periods have been measured using multiple interrupts from shorter inter- rupt intervals. each timer interrupt required servicing, with each accompanying interruption slowing system operation. by using the rtc subsecond timer as a long-period timer, only one interrupt is needed, elimi- nating the performance hit associated with using a shorter timer. an internal crystal oscillator clocks the rtc using inte- grated 6pf load capacitors, and yields the best perfor- mance when mated with a 32.768khz crystal rated for a 6pf load. no external load capacitors are required. higher accuracy can be obtained by supplying an external clock source to the rtc. programmable timers the microcontroller incorporates three instances of the16-bit programmable timer/counter b peripheral, denoted tb0, tb1, and tb2. they can be used in counter/timer/capture/compare/pwm functions, allow- ing precise control of internal and external events. these timer/counters support clock input prescaling and set/reset/toggle pwm/output control functionality not found on other maxq timer implementations. a new register, tbc, supports certain pwm/output control functions in some implementations. a distinguishing characteristic of timer/counter b is that its count mode type start bits data bits stop bit mode 0 synchronous 8 mode 1 asynchronous 1 8 1 mode 2 asynchronous 1 8 + 1 1 mode 3 asynchronous 1 8 + 1 1 table 1. serial port operating characteristics downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 27 ranges from 0000h to the value stored in the 16-bit cap-ture/reload register (tbr), whereas in other implemen- tations (e.g., timer 1) the count ranges from the value in the reload register to ffffh. these timers are fully described in the maxq family user? guide . timer b operational modes include the following:?autoreload ?autoreload using external pin ?capture using external pin ?up/down count using external pin ?up-count pwm/output ?up/down pwm/output ?clock output on tbb pin watchdog timer an internal watchdog timer greatly increases system reli-ability. the timer resets the device if software execution is disturbed. the watchdog timer is a free-running counter designed to be periodically reset by the applica- tion software. if software is operating correctly, the counter is periodically reset and never reaches its maxi- mum count. however, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. this protects the system against electrical noise or electrostatic discharge (esd) upsets that could cause uncontrolled processor operation. the internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. the watchdog timer is controlled through bits in the wdcn register. its timeout period can be set to one of four programmable intervals ranging from 2 12 to 2 21 system clocks in its default mode, allowing flexibility tosupport different types of applications. the interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. at 8mhz, watchdog timeout periods can be programmed from 512? to 67s, depending on the system clock mode. hardware multiplier the internal hardware multiplier supports high-speedmultiplications. the multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle with the support of a 48-bit accumulator. the multiplier is a fixed-point arithmetic unit. the operands can be either signed or unsigned numbers, but the data type must be defined by the application software prior to loading the operand registers. seven different multiply operations can be performedwithout requiring direct intervention of the microcon- troller core. these include the following: ?unsigned 16-bit multiplication ?unsigned 16-bit multiplication and accumulation ?unsigned 16-bit multiplication and subtraction ?signed 16-bit multiplication ?signed 16-bit multiplication and negate ?signed 16-bit multiplication and accumulation ?signed 16-bit multiplication and subtraction each of these operations is controlled and accessed through six sfr registers. the 8-bit multiplier control register (mcnt) selects the operation, data type, operand count, optional hardware-based square func- tion, write option on the mc register, the overflow flag, and the clear control for operand registers and accu- mulator. loading and unloading of the data is achieved through five 16-bit sfr registers. only one cycle is needed for computation. this means that the result of an operation is ready in the next cycle immediately following the loading of the last operand. back-to-back operations can be performed without wait states between operations, independent of data type and operand count. analog-to-digital converter the maxq2010 contains a 12-bit successive approxi-mation analog-to-digital converter (adc) with an analog mux (figure 7). the mux selects the adc input from eight single-ended channels or four differential chan- nels. an internal precision bandgap reference can be used for the adc reference voltage, or the reference voltage can be externally driven. additionally, the ana- log supply voltage (avdd) can also be used as the voltage reference. the adc runs off a 2.7v to 3.6v power supply and at a conversion rate up to 300ksps. the adc block includes a 12-bit sar core, adc con- trols, a reference generator, and a circular block of six- teen 12-bit data buffers. the adc is controlled by sfr registers. an autoscan feature allows the user to select up to eight sampling channels for storage in the 16 memory locations. there are two conversion modes: single-sequence mode and continuous-sequence mode. the adc? internal power-management system auto- matically powers down when the conversion(s) are done (adconv = 0). the start conversion bit, adconv, is used to start all conversion processes. if the adc power-management override bit is cleared downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 28 ______________________________________________________________________________________ (adpmo = 0), the adc waits for 20 adcclk beforestarting the first conversion. this allows the adc time to set up. if adpmo = 1, an adc conversion is initiated as soon as adconv is set to 1. adc operation is aborted upon entry into pmm or stop mode. the adconv bit is set at the beginning of the conver- sion process and remains set until the conversion process is finished. in single-sequence mode, this bit remains set until the adc has finished conversion on the last channel in the sequence. in continuous mode, the adconv bit remains set until the continuous mode is stopped. writing a 0 to the adconv bit stops adc operation at the completion of the current adc conver- sion. the new data is written to the data buffer. an a/d conversion takes 16 adcclk cycles to com- plete. three of the 16 adcclk cycles are used for sample acquisition. the adcclk is derived from the system clock with divide ratio defined by the adc clock divider bits (adcclk). therefore, with 16 adcclk to acquire one data, the fastest adc rate = sysclk/16 (adcclk = 0h, adacqen = 0h). with a 10mhz sys- tem clock, this is theoretically equivalent to 10mhz/16 value msps. note, however, that the adc conversion is limited to 300ksps. if the adc data-available interrupt is enabled (addaie = 1), an interrupt is generated to the cpu when addai = 1. once set, the addai flag can be cleared by soft- ware writing a 0 or at the start of a conversion process when adconv is set to 1. the data-available interrupt flag (addai) can optionally be set by using the adc data-available interrupt interval bits (addainv). the addai can be set in 1, 2, 3, 4, 5, 6, 7, 8, 12, or 16 sam-ples intervals. for a sequence that uses only one con- figuration register, setting addainv = 00 generates an interrupt with the same interval as addainv = 01, both of which set the addai at every adc sample. when the addai is set, the last memory location written by adc will also be written to addaddr. lcd controller the maxq2010 microcontroller incorporates an lcdcontroller that interfaces to common low-voltage dis- plays. by incorporating the lcd controller into the microcontroller, the design requires only an lcd glass rather than a considerably more expensive lcd mod- ule. every character in an lcd glass is composed of one or more segments, each of which is activated by selecting the appropriate segment and common signal. the microcontroller can multiplex combinations of up to 43 segment outputs (seg0 to seg42) and four com- mon signal outputs (com0 to com3). unused segment outputs can be used as general-purpose port pins. the segments are easily addressed by writing to dedi- cated display memory. once the lcd controller set- tings and display memory have been initialized, the 21-byte display memory is periodically scanned, and the segment and common signals are generated auto- matically at the selected display frequency. no addi- tional processor overhead is required while the lcd controller is running. unused display memory can be used for general-purpose storage. the design is further simplified and cost reduced by the inclusion of software-adjustable internal voltage- input multiplexer and track/hold 12-bit sar internal reference external reference avdd adc reference adc control an7 avdd avss adc interrupt an6 an5 an4 an3 an2 an1 an0 figure 7. adc block diagram downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 29 dividers to control display contrast, using either v ddio or an external voltage. if desired, contrast can also becontrolled with an external resistance. the features of the lcd controller include the following: automatic lcd segment and common-drive signal generation ?four display modes supported: static (com0)1/2 duty multiplexed with 1/2 bias voltages (com[0:1]) 1/3 duty multiplexed with 1/3 bias voltages (com[0:2]) 1/4 duty multiplexed with 1/3 bias voltages (com[0:3]) up to 43 segment outputs and four common-signal outputs ?21 bytes (168 bits) of display memory ?flexible lcd clock source, selectable from 32khz or hfclk/512 ?adjustable frame frequency internal voltage-divider resistors eliminate require- ment for external components ?internal adjustable resistor allows contrast adjustment without external components a simple lcd-segmented glass interface exampledemonstrates the minimal hardware required to inter- face to a maxq2010 microcontroller. a two-character lcd is controlled, with each character containing seven segments plus decimal point. the lcd controller is configured for 1/2 duty-cycle operation, meaning the active segment is controlled using a combination ofsegment signals and com0 or com1 signals are used to select the active display. see figure 8. in-circuit debug embedded debugging capability is available throughthe jtag-compatible tap. embedded debug hardware and embedded rom firmware provide in-circuit debug- ging capability to the user application, eliminating the need for an expensive in-circuit emulator. figure 9 shows a block diagram of the in-circuit debugger. the in-circuit debug features include the following: ?a hardware debug engine. ?a set of registers able to set breakpoints on register, code, or data accesses. a set of debug service routines stored in the utility rom. the embedded hardware debug engine is an indepen-dent hardware block in the microcontroller. the debug engine can monitor internal activities and interact with selected internal registers while the cpu is executing user code. collectively, the hardware and software fea- tures allow two basic modes of in-circuit debugging: background mode allows the host to configure and set up the in-circuit debugger while the cpu contin-ues to execute the application software at full speed. debug mode can be invoked from background mode. ?debug mode allows the debug engine to take control of the cpu, providing read/write access to internal reg-isters and memory, and single-step trace operation. seg0 seg1seg2 seg3 com0 seg[0:7] connected to dark grey segments com1 connected to light grey segments seg4seg5 seg6 seg7 maxq2010 figure 8. two-character, 1/2 duty, lcd interface example downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 30 ______________________________________________________________________________________ applications information the low-power, high-performance risc architecture ofthis device makes it an excellent fit for many portable or battery-powered applications that require cost-effective computing. the high-throughput core is complemented by a 16-bit hardware multiplier-accumulator, allowing the implementation of sophisticated computational algorithms. applications benefit from a wide range of peripheral interfaces, allowing the microcontroller to communicate with many external devices. with integrat- ed lcd support of up to 160 segments, applications can support complex user interfaces. displays are dri- ven directly with no additional external hardware required. contrast can be adjusted using a built-in, adjustable resistor. the simplified architecture reduces component count and board space, critical factors in the design of portable systems. the maxq2010 is ideally suited for applications such as medical instrumentation, portable blood-glucose equipment, and data-collection devices. for blood-glu- cose measurement, the microcontroller integrates an spi interface that directly connects with analog front- ends for measuring test strips. grounds and bypassing careful pcb layout significantly minimizes noise on theanalog inputs, resulting in less noise on the digital i/o that could cause improper operation. the use of multi-layer boards is essential to allow the use of dedicated power planes. the area under any digital components should be a continuous ground plane if possible. keep any bypass capacitor leads short for best noise rejec- tion and place the capacitors as close to the leads of the devices as possible. separate ground areas must be provided for the analog (agnd) and digital (dgnd) portions, connected together at a single point. cmos design guidelines for any semiconductor require that no pin be taken above v dvdd or below dgnd. violation of this guideline can result in a hard failure(damage to the silicon inside the device) or a soft fail- ure (unintentional modification of memory contents). voltage spikes above or below the device? absolute maximum ratings can potentially cause a devastating ic latchup. microcontrollers commonly experience negative volt- age spikes through either their power pins or general- purpose i/o pins. negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. system designers must protect components against these transients that can corrupt system memory. tap controller cpu debug engine debug service routines (utility rom) control breakpoint address data tms tck tdi tdo maxq2010 figure 9. in-circuit debugger downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 31 pin configuration an3 p0.5/seg5/int5 1 75 an4 p0.4/seg4/int4 2 74 an5 p0.3/seg3/int3 3 73 an6 p0.2/seg2/int2 4 72 an7 p0.1/seg1/int1 5 71 n.c. com0 7 69 p5.0/int8/tb0b/rx0 com1/seg42 8 68 p5.1/int9/tb0a/tx0 com2/seg41 9 67 n.c. p6.5/int20/tb1a/tx1 25 51 top view avref 6 70 p0.0/seg0/int0 hfxout 11 65 p4.7/seg39 hfxin 12 64 p4.6/seg38 dvdd 13 63 p4.5/seg37 p5.2/int10/sqw 15 61 p4.3/seg35 p5.3/int11/ssel 16 60 p4.2/seg34 p5.4/int12/mosi 17 59 p4.1/seg33 dgnd 10 66 com3/seg40 n.c. 14 62 p4.4/seg36 p5.5/int13/sclk 18 58 p4.0/seg32 p5.6/int14/miso 19 57 p3.7/seg31 p2.0/seg16 20 56 p3.6/seg30 p2.2/seg18 22 54 p3.4/seg28 p2.3/seg19 23 53 p6.7/int22/tb2a/sda p2.4/seg20 24 52 p6.6/int21/tb2b/scl p2.1/seg17 21 55 p3.5/seg29 lqfp 26 100 n.c. n.c. 27 99 n.c. regout 28 98 p6.4/int19/tb1b/rx1 regout 29 97 p6.3/int18/tdo n.c. 30 96 p6.2/int17/tms dvdd 31 95 p6.1/int16/tdi dgnd 32 94 p6.0/int15/tck p0.6/seg6/int6 33 93 p0.7/seg7/int7 p3.3/seg27 34 92 p3.2/seg26 rst 35 91 p1.0/seg8 p3.1/seg25 36 90 p1.1/seg9 p3.0/seg24 37 89 p1.2/seg10 n.c. 38 88 p1.3/seg11 n.c. 39 87 p1.4/seg12 n.c. 40 86 p1.5/seg13 dvdd 41 85 dgnd p1.6/seg14 42 84 p1.7/seg15 v adj 43 83 n.c. v lcd2 44 82 avdd v lcd1 45 81 32kin v lcd 46 80 32kout p2.7/seg23 47 79 agnd p2.6/seg22 48 78 an0 p2.5/seg21 49 77 an1 n.c. 50 76 n.c. an2 + maxq2010 downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface 32 ______________________________________________________________________________________ typical application circuit avddagnd dvdd dgnd an0 an1 an2 an3 an4 an5 an6 an7 rst 32kin 32kout avref optional external reference com3 com2 com1 com0 rx0 tx0 rx1 tx1 up to 40 seg pins up to 55 digital i/o pins jtag pins 10nf 32.768khz hfxin optional hfxout 10mhz 22pf 1 f 22pf 1k regout 1 f lcd segment pins 160-segment lcd display scl sda ssel mosi sclk miso serial 0serial 1 host interface maxq2010 rs-232 transceiver max3233e four current sources capable of sinking or sourcing current* *application dependent. jtag interface host interface ds4404 dual audio taper potentiometer with pushbutton control* ds1802 downloaded from: http:///
additional documentation designers must have four documents to fully use all thefeatures of this device. this data sheet contains pin descriptions, feature overviews, and electrical specifi- cations. errata sheets contain deviations from pub- lished specifications. the user? guides offer detailed information about device features and operation. the following documents can be downloaded from www.maxim-ic.com/microcontrollers . this maxq2010 data sheet, which contains electri- cal/timing specifications and pin descriptions. the maxq2010 revision-specific errata sheet ( www.maxim-ic.com/errata ). ?the maxq family user's guide , which contains detailed information on core features and operation, includingprogramming ( www.maxim-ic.com/maxqug ). ?the maxq family user's guide: maxq2010 supplement , which contains detailed information on features spe- cific to the maxq2010. development and technical support maxim and third-party suppliers provide a variety ofhighly versatile, affordably priced development tools for this microcontroller, including the following: ?compilers ?in-circuit emulators ?integrated development environments (ides) jtag-to-serial converters for programming and debugging a partial list of development tool vendors can be foundat www.maxim-ic.com/maxq_tools . for technical support, go to https://support.maxim- ic.com/micro . maxq2010 16-bit mixed-signal microcontroller with lcd interface ______________________________________________________________________________________ 33 package type package code document no. 100 lqfp 21-0297 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . part program memory (kb) data memory (kb) lcd segments adc channels adc resolution MAXQ2010-RFX+ 64 2 160 8 12 selector guide downloaded from: http:///
maxq2010 16-bit mixed-signal microcontroller with lcd interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 34 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/08 initial release. updated the title to include lcd interface. all corrected the axis titles for toc2 in the tpical operating characteristics section. 14 1 12/08 added the i 2 c bus and serial peripheral interface (spi) sections. 26 downloaded from: http:///

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